The present invention relates to a process of fabricating semiconductor devices and, more particularly, to a process of forming a crystalline semiconductor on an insulating film through solid-phase crystalline growth to form a semiconductor device on that crystalline semiconductor.
In order to realize an LSI capable of superhigh speed operations and having a large scale integration, it has been proposed to fabricate an SOI structure by various processes. The "SOI" is the abbreviation of "Silicon On Insulator" and implies formation of a high-quality crystalline (e.g., single-crystal or large-grain polycrystalline) Si film. Of SOI fabricating techniques, the technique making use of the solid-phase epitaxial growth is accepted as one of the most promising techniques as a process best fit for lamination and high integration because it can form single-crystal film at a low temperature. In order to form a single-crystal film having a sufficient area, however, this process in required to add an electrically active impurity to an amorphous Si film up to its solid solubility limit, as has been discussed on pp. 268 to 270, Vol. 46 (1985), Applied Physics Letters. This raises a problem that a variety of semi-conductor elements having many regions doped with impurities in various concentrations cannot be formed in a single-crystal film containing such much impurities.
The most typical one of the SOI techniques utilizing the solid-phase epitaxial growth comprises, as schematically shown in FIG. 10, the steps of: forming a SiO.sub.2 film 2 on a single-crystal Si substrate 1; depositing an amorphous Si film 3 thereon by the electron beam evaporation or the like; and subsequently heating the amorphous Si film 3 to about 600.degree. C. to crystallize it (for the solid-phase epitaxial growth) in the directions indicated by arrows 5. Since the SiO.sub.2 film 2 is formed at places with apertures 7, the amorphous Si film 3 makes contact with the single-crystal Si substrate 1 through those apertures 7. When heated, the contacting portions of the single-crystal substrate 1 act as seed crystals from which the crystallizations start. The crystal growths proceed before long onto the SiO.sub.2 film 2 so that SOI regions 6 having the same crystal orientation as that of the substrate 1 are formed. After some heating time period (e.g., about 10 hours), on the other hand, the amorphous Si film 3 polycrystallize at places apart from the seed crystal regions 7 independently of the above-specified crystal growths. Since the polycrystalline Si film 8 thus formed blocks the aforementioned crystal growths, as shown in FIG. 11, the areas of the SOI regions 6 finally obtained are determined depending upon the balance between the rate of the aforementioned crystal growths and the time period required for that polycrystallization. In case an amorphous Si film containing no impurity is used, the crystal growth rate is about 1.0.times.10.sup.-8 cm/s, whereas the time period required for forming the polycrystalline Si film 8 is about 10 hours. The SOI regions 6 obtained are located within a range of about 4 microns from the ends of the seed crystal regions 7. This behavior is shown in FIG. 13. This extension is not sufficient for fabricating the semiconductor devices. A proposal made to solve this problem is the aforementioned impurity doping method. This method uses an amorphous Si film to which an electrically active impurity such as P, B or As is added up to its solid solubility limit. Then, as shown in FIG. 13, the crystal growth rate is increased to enlarge the SOI regions 6. In case P is added, for example, SOI regions of about 24 microns are obtained by about 10 hours later when the polycrystalline Si film begins to be formed. According to this method, however, the amorphous Si film has too high an impurity concentration to form the device in it although the extension raises no problem. At present, therefore, it has been tried, as shown in FIG. 12, to form the SOI regions, to subsequently deposit the single-crystal Si film having a low impurity concentration all over the surfaces on the SO regions by molecular beam epitaxial (i.e., MBE) growth, and to form an MS transistor therein. With this construction, however, a film 9 where the device is formed is underlaid with an SOI film 4 and the polycrystalline Si films 8 to result in the losses of the major merits of the SOI structure: (1) the merit that the element operations are speeded up; and (2) the merit that the element separation is facilitated to enable the high integration, both of which could have been obtained in the presence of the underlying insulating film.